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rev.1.00 jan. 13, 2005 page 1 of 13 RD74VT1G245 bus transceiver with 3?state output / dual supply voltage translator rej03d0494?0100 rev.1.00 jan. 13, 2005 description the RD74VT1G245 has one buffer in a 6 pin package. when dir is high, data is transferred from the a inputs to the b outputs, and when dir is low, data is transferred from the b inputs to the a outputs. and this product has two terminals (v cca , v ccb ), v cca is connected with control input and a bus side v ccb is connected with b bus side. v cca and v ccb are isolated. the a port is designed to track v cca , which accepts voltages from 1. 2v to 3.6v, and the b port is designed to track v ccb , which operation at 1.2v to 3.6v. therefore, bidirectional board voltage conversion is possible. low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. features ? this product function as level shift transceiver that change v cca input level to v ccb output level, v ccb input level to v cca output level by providing different supply voltage to v cca and v ccb . ? supply voltage range: v cca = 1.2 to 3.6 v v ccb = 1.2 to 3.6 v ? operating temperature range: ? 40 to +85c ? control input v i(max) = 3.6 v (@v cca = 0 to 3.6 v) ? a bus side input outputs v i/o (max) = 3.6 v (@v cca = 0 v or output off state) ? b bus side input outputs v i/o (max) = 3.6 v (@v ccb = 0 v or output off state) ? high output current a bus side: 2 ma (@v cca = 1.2 v) b bus side: 2 ma (@v ccb = 1.2 v) 4 ma (@v cca = 1.50.1 v) 4 ma (@v ccb = 1.50.1 v) 6 ma (@v cca = 1.80.15 v) 6 ma (@v ccb = 1.80.15 v) 18 ma (@v cca = 2.50.2 v) 18 ma (@v ccb = 2.50.2 v) 24 ma (@v cca = 3.30.3 v) 24 ma (@v ccb = 3.30.3 v) ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) RD74VT1G245cle wcsp?6 pin tbs?6av cl e (3,000 pcs/reel)
RD74VT1G245 rev.1.00 jan. 13, 2005 page 2 of 13 article indication v y y m marking year code month code function table inputs dir operation l b a h a b h: high level l: low level pin arrangement (bottom view) (top view) b 16 2 34 gnd height 0.5 mm 0.5 mm pitch 0.23 mm 6?ball (cl) 0.9 mm 1.4 mm av ccb dir v cca 5 pin#1 index
RD74VT1G245 rev.1.00 jan. 13, 2005 page 3 of 13 logic diagram a b dir absolute maximum ratings item symbol ratings unit conditions supply voltage range v cca , v ccb ?0.5 to 4.6 v input voltage range *1 v i ?0.5 to 4.6 v dir ?0.5 to v cca +0.5 a port output: ?h? or ?l? ?0.5 to 4.6 a port output: ?z? or v cca : off ?0.5 to v ccb +0.5 b port output: ?h? or ?l? input/output voltage range *1, 2 v i/o ?0.5 to 4.6 v b port output: ?z? or v ccb : off input clamp current i ik ?50 ma v i < 0 ?50 v o < 0 output clamp current i ok 50 ma v o > v cc +0.5 continuous output current i o 50 ma continuous output current v cc or gnd i cca , i ccb , i gnd 100 ma package thermal impedance ja 123 c/w storage temperature tstg ?65 to 150 c notes: the absolute maximum ratings are values, which mu st not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. the input and output voltage rati ngs may be exceeded if the input and output clamp-current ratings are observed. 2. this value is limited to 4.6 v maximum.
RD74VT1G245 rev.1.00 jan. 13, 2005 page 4 of 13 recommended operating conditions item symbol ratings unit conditions v cca 1.2 to 3.6 supply voltage range v ccb 1.2 to 3.6 v v i 0 to 3.6 v dir 0 to 3.6 a port output: ?h? or ?l? 0 to v cca a port output: ?z? or v cca : off 0 to 3.6 b port output: ?h? or ?l? input/output voltage v i/o 0 to v ccb v b port output: ?z? or v ccb : off ?2 v cca = 1.2 v ?4 v cca = 1.50.1 v ?6 v cca = 1.80.15 v ?18 v cca = 2.50.2 v i oha ?24 ma v cca = 3.30.3 v ?2 v ccb = 1.2 v ?4 v ccb = 1.50.1 v ?6 v ccb = 1.80.15 v ?18 v ccb = 2.50.2 v i ohb ?24 ma v ccb = 3.30.3 v 2 v cca = 1.2 v 4 v cca = 1.50.1 v 6 v cca = 1.80.15 v 18 v cca = 2.50.2 v i ola 24 ma v cca = 3.30.3 v 2 v ccb = 1.2 v 4 v ccb = 1.50.1 v 6 v ccb = 1.80.15 v 18 v ccb = 2.50.2 v output current i olb 24 ma v ccb = 3.30.3 v input transition rise or fall time ? t / ? v 10 ns / v operation free-air temperature ta ?40 to 85 c
RD74VT1G245 rev.1.00 jan. 13, 2005 page 5 of 13 electrical characteristics (ta = ? 40 to 85c) item symbol v cca (v) * v ccb (v) * min typ max unit test conditions 1.2 v cca 0.75 ? ? 1.50.1 v cca 0.70 ? ? 1.80.15 v cca 0.65 ? ? 2.50.2 1.6 ? ? v iha 3.30.3 1.2 to 3.6 2.0 ? ? v a port control input 1.2 v ccb 0.75 ? ? 1.50.1 v ccb 0.70 ? ? 1.80.15 v ccb 0.65 ? ? 2.50.2 1.6 ? ? v ihb 1.2 to 3.6 3.30.3 2.0 ? ? v b port 1.2 ? ? v cca 0.25 1.50.1 ? ? v cca 0.30 1.80.15 ? ? v cca 0.35 2.50.2 ? ? 0.7 v ila 3.30.3 1.2 to 3.6 ? ? 0.8 v a port control input 1.2 ? ? v ccb 0.25 1.50.1 ? ? v ccb 0.30 1.80.15 ? ? v ccb 0.35 2.50.2 ? ? 0.7 input voltage v ilb 1.2 to 3.6 3.30.3 ? ? 0.8 v b port 1.2 to 3.6 1.2 to 3.6 v cc ? 0.2 ? ? i oh = ?100 a 1.2 1.2 0.9 ? ? i oh = ?2 ma 1.50.1 1.50.1 1.1 ? ? i oh = ?4 ma 1.80.15 1.80.15 1.25 ? ? i oh = ?6 ma 2.50.2 2.50.2 1.7 ? ? i oh = ?18 ma v oh 3.30.3 3.30.3 2.2 ? ? v i oh = ?24 ma 1.2 to 3.6 1.2 to 3.6 ? ? 0.2 i ol = 100 a 1.2 1.2 ? ? 0.3 i ol = 2 ma 1.50.1 1.50.1 ? ? 0.3 i ol = 4 ma 1.80.15 1.80.15 ? ? 0.3 i ol = 6 ma 2.50.2 2.50.2 ? ? 0.6 i ol = 18 ma output voltage v ol 3.30.3 3.30.3 ? ? 0.55 v i ol = 24 ma input current i in 3.6 3.6 ?1.5 ? 1.5 a v in = gnd or v cca control input off state output current i oz 3.6 3.6 ?1.5 ? 1.5 a v in = v ih or v il output leakage current i off 0 0 ? ? 1.5 a v in , v out = 0 to 3.6 v i cca 1.2 to 3.6 1.2 to 3.6 ?3.0 ? 3.0 i o(a port) = 0 v in = v ccb or gnd quiescent supply current i ccb 1.2 to 3.6 1.2 to 3.6 ?3.0 ? 3.0 a i o(b port) = 0 v in = v cca or gnd ? i cca 3.6 3.6 ? ? 250 a port or control v cca ?0.6 (1 input) increase in icc per input ? i ccb 3.6 3.6 ? ? 250 a b port v ccb ?0.6 (1 input) input capacitance c in 3.3 3.3 ? 3.5 ? pf v in = v cc or gnd input/output capacitance c i/o 3.3 3.3 ? 6.0 ? pf v o = v cc or gnd note: for conditions shown as min or max, use the appr opriate values under recommended operating conditions.
RD74VT1G245 rev.1.00 jan. 13, 2005 page 6 of 13 switching characteristics v cca = 3.30.3 v ta = ?40 to 85c v ccb = 1.2 v v ccb = 1.50.1 v v ccb = 1.80.15 v v ccb = 2.50.2 v v ccb = 3.30.3 v item symbol from (input) to (output) typ min max min max min max min max unit test conditions t plh 9.1 2.0 8.8 1.5 5. 8 1.0 4.0 1.0 3.2 t phl a b 9.1 2.0 8.8 1.5 5. 8 1.0 4.0 1.0 3.2 t plh 4.0 1.0 4.2 1.0 3. 8 1.0 3.4 1.0 3.2 propagation delay time t phl b a 4.0 1.0 4.2 1.0 3. 8 1.0 3.4 1.0 3.2 ns c l = 15pf r l = 2.0k ? t hz 4.0 1.0 4.5 1.0 4. 5 1.0 4.5 1.0 4.5 t lz dir a 4.0 1.0 4.5 1.0 4. 5 1.0 4.5 1.0 4.5 t hz 11.2 2.0 10.2 1.5 8. 0 1.0 6.0 1.0 5.5 output disable time t lz dir b 11.2 2.0 10.2 1.5 8. 0 1.0 6.0 1.0 5.5 ns c l = 15pf r l = 2.0k ? t zh *1 15.2 ? 14.4 ? 11.8 ? 9.4 ? 8.7 t zl *1 dir a 15.2 ? 14.4 ? 11.8 ? 9.4 ? 8.7 t zh *1 13.1 ? 13.3 ? 10.3 ? 8.5 ? 7.7 output enable time t zl *1 dir b 13.1 ? 13.3 ? 10.3 ? 8.5 ? 7.7 ns c l = 15pf r l = 2.0k ? note: 1. the enable time is a calculated value, derived us ing the formula shown in the section entitled enable times on page 12. v cca = 2.50.2 v ta = ?40 to 85c v ccb = 1.2 v v ccb = 1.50.1 v v ccb = 1.80.15 v v ccb = 2.50.2 v v ccb = 3.30.3 v item symbol from (input) to (output) typ min max min max min max min max unit test conditions t plh 9.5 2.0 9.2 1.5 6. 0 1.0 4.2 1.0 3.4 t phl a b 9.5 2.0 9.2 1.5 6. 0 1.0 4.2 1.0 3.4 t plh 4.7 1.0 4.8 1.0 4. 6 1.0 4.2 1.0 4.0 propagation delay time t phl b a 4.7 1.0 4.8 1.0 4. 6 1.0 4.2 1.0 4.0 ns c l = 15pf r l = 2.0k ? t hz 4.2 1.0 4.7 1.0 4. 7 1.0 4.7 1.0 4.7 t lz dir a 4.2 1.0 4.7 1.0 4. 7 1.0 4.7 1.0 4.7 t hz 11.2 2.0 10.6 1.5 8. 4 1.0 6.0 1.0 6.0 output disable time t lz dir b 11.2 2.0 10.6 1.5 8. 4 1.0 6.0 1.0 6.0 ns c l = 15pf r l = 2.0k ? t zh *1 15.9 ? 15.4 ? 13.0 ? 10.2 ? 10.0 t zl *1 dir a 15.9 ? 15.4 ? 13.0 ? 10.2 ? 10.0 t zh *1 13.7 ? 13.9 ? 10.7 ? 8.9 ? 8.1 output enable time t zl *1 dir b 13.7 ? 13.9 ? 10.7 ? 8.9 ? 8.1 ns c l = 15pf r l = 2.0k ? note: 1. the enable time is a calculated value, derived us ing the formula shown in the section entitled enable times on page 12.
RD74VT1G245 rev.1.00 jan. 13, 2005 page 7 of 13 switching characteristics (cont.) v cca = 1.8 0.15 v ta = ?40 to 85c v ccb = 1.2 v v ccb = 1.50.1 v v ccb = 1.80.15 v v ccb = 2.50.2 v v ccb = 3.30.3 v item symbol from (input) to (output) typ min max min max min max min max unit test conditions t plh 9.8 2.0 9.6 1.5 6. 5 1.0 4.6 1.0 3.8 t phl a b 9.8 2.0 9.6 1.5 6. 5 1.0 4.6 1.0 3.8 t plh 6.4 1.5 7.2 1.5 6. 5 1.5 6.0 1.5 5.8 propagation delay time t phl b a 6.4 1.5 7.2 1.5 6. 5 1.5 6.0 1.5 5.8 ns c l = 15pf r l = 2.0k ? t hz 5.5 1.5 7.5 1.5 7. 5 1.5 7.5 1.5 7.5 t lz dir a 5.5 1.5 7.5 1.5 7. 5 1.5 7.5 1.5 7.5 t hz 12.0 2.0 11.5 1.5 9. 2 1.0 7.2 1.0 7.0 output disable time t lz dir b 12.0 2.0 11.5 1.5 9. 2 1.0 7.2 1.0 7.0 ns c l = 15pf r l = 2.0k ? t zh *1 18.4 ? 18.7 ? 15.7 ? 13.2 ? 12.8 t zl *1 dir a 18.4 ? 18.7 ? 15.7 ? 13.2 ? 12.8 t zh *1 15.3 ? 17.1 ? 14.0 ? 12.1 ? 11.3 output enable time t zl *1 dir b 15.3 ? 17.1 ? 14.0 ? 12.1 ? 11.3 ns c l = 15pf r l = 2.0k ? note: 1. the enable time is a calculated value, derived us ing the formula shown in the section entitled enable times on page 12. v cca = 1.5 0.1 v ta = ?40 to 85c v ccb = 1.2 v v ccb = 1.50.1 v v ccb = 1.80.15 v v ccb = 2.50.2 v v ccb = 3.30.3 v item symbol from (input) to (output) typ min max min max min max min max unit test conditions t plh 10.0 2.0 10.5 1.5 7. 2 1.0 4.8 1.0 4.2 t phl a b 10.0 2.0 10.5 1.5 7. 2 1.0 4.8 1.0 4.2 t plh 8.0 2.0 10.5 2.0 9. 6 2.0 9.2 2.0 8.8 propagation delay time t phl b a 8.0 2.0 10.5 2.0 9. 6 2.0 9.2 2.0 8.8 ns c l = 15pf r l = 2.0k ? t hz 6.0 2.0 10.0 2.0 10. 0 2.0 10.0 2.0 10.0 t lz dir a 6.0 2.0 10.0 2.0 10. 0 2.0 10.0 2.0 10.0 t hz 12.5 2.0 12.7 1.5 12. 0 1.0 10.7 1.0 7.5 output disable time t lz dir b 12.5 2.0 12.7 1.5 12. 0 1.0 10.7 1.0 7.5 ns c l = 15pf r l = 2.0k ? t zh *1 20.5 ? 23.2 ? 21.6 ? 19.9 ? 16.3 t zl *1 dir a 20.5 ? 23.2 ? 21.6 ? 19.9 ? 16.3 t zh *1 16.0 ? 20.5 ? 17.2 ? 14.8 ? 14.2 output enable time t zl *1 dir b 16.0 ? 20.5 ? 17.2 ? 14.8 ? 14.2 ns c l = 15pf r l = 2.0k ? note: 1. the enable time is a calculated value, derived us ing the formula shown in the section entitled enable times on page 12.
RD74VT1G245 rev.1.00 jan. 13, 2005 page 8 of 13 switching characteristics (cont.) v cca = 1.2 v ta = ?40 to 85c v ccb = 1.2 v v ccb = 1.50.1 v v ccb = 1.80.15 v v ccb = 2.50.2 v v ccb = 3.30.3 v item symbol from (input) to (output) typ typ typ typ typ unit test conditions t plh 10.5 8.0 6.4 4.7 4.0 t phl a b 10.5 8.0 6.4 4.7 4.0 t plh 10.5 10.0 9.8 9.5 9.1 propagation delay time t phl b a 10.5 10.0 9.8 9.5 9.1 ns c l = 15pf r l = 2.0k ? t hz 8.0 8.0 8.0 8.0 8.0 t lz dir a 8.0 8.0 8.0 8.0 8.0 t hz 13.5 10.5 9.5 7.5 7.5 output disable time t lz dir b 13.5 10.5 9.5 7.5 7.5 ns c l = 15pf r l = 2.0k ? t zh *1 24.0 20.5 19.3 17.0 16.6 t zl *1 dir a 24.0 20.5 19.3 17.0 16.6 t zh *1 18.5 16.0 14.4 12.7 12.0 output enable time t zl *1 dir b 18.5 16.0 14.4 12.7 12.0 ns c l = 15pf r l = 2.0k ? note: 1. the enable time is a calculated value, derived us ing the formula shown in the section entitled enable times on page 12. operating characteristics ta = 25c item symbol v cca (v) v ccb (v) min typ max unit test conditions power dissipation capacitance c pd 3.3 3.3 ? 12 ? pf f = 10 mhz c l = 0 power?up considerations level?translation devices offer an opportunity for successful mixed?voltage signal design. a proper power?up sequence always should be followed to a void excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. take these precautions to guard against such power?up problems. 1. connect ground before any supply voltage is applied. 2. next, power up the control side of the device. (power up of v cca is first. next power up is v ccb ) 3. depending on the direction of the data path, dir can be high or low. if dir high is needed (a data to b bus), ramp it with v cca . otherwise, dir low is needed (b data to a bus), ramp it with gnd.
RD74VT1G245 rev.1.00 jan. 13, 2005 page 9 of 13 test circuit open s1 c l = 15 pf *1 2 k ? load circuit for outputs 2 k ? see under table gnd symbol t / t plh phl t / t zh hz t / t zl lz s1 open gnd note: 1. c l includes probe and jig capacitance. 2 v cc
RD74VT1G245 rev.1.00 jan. 13, 2005 page 10 of 13 v ref v ref v ref v ref input output waveforms ? 1 waveforms ? 2 v h v l t zl t lz t phl t zh t hz v oh v ol output a or b waveform?1 output a or b waveform?2 input dir gnd v ih t plh v oh v ol v oh v ol tr 10 % 10 % 10 % 10 % 90 % 90 % 90 % 90 % tf v ref v ref v ref v ref gnd v ih tr 10 % 10 % 90 % 90 % tf notes: 1. input waveform : prr 10 mhz, zo = 50 ? , duty cycle 50%. 2. waveform ? 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform ? 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. the output are measured one at a time with one transition per measurement. v ref v / v hl v ih t / t rf v h = v oh -0.15 v v l = v ol +0.15 v v h = v oh -0.1 v v l = v ol +0.1 v v h = v oh -0.15 v v l = v ol +0.15 v v h = v oh -0.3 v v l = v ol +0.3 v v cc v cc v cc 1/2 v cc 1/2 v cc 1/2 v cc 1/2 v cc v cc 2.0 ns 2.0 ns 2.0 ns 2.0 ns v = 2.5 0.2 v cc v = 3.3 0.3 v cc v = 1.8 0.15 v cc v = 1.2 v, 1.5 0.1 v cc symbol
RD74VT1G245 rev.1.00 jan. 13, 2005 page 11 of 13 application information figure 1 is an example circuit of the RD74VT1G245 being used in a bidirectional logic level?shifting application. 6 1 5 4 2 3 system?1 system?2 v cc1 v cc1 v cc2 v cc2 figure 1. bidirectional logic level?shifting application pin description pin name function description 1 dir dir the gnd (low?level) dete rmines b?port to a?port direction 2 a out output level depends on v cc1 voltage 3 gnd gnd device gnd 4 b in input threshold value depends on v cc2 voltage 5 v ccb v cc2 system?2 supply voltage (1.2v to 3.6v) 6 v cca v cc1 system?1 supply voltage (1.2v to 3.6v)
RD74VT1G245 rev.1.00 jan. 13, 2005 page 12 of 13 application information (cont.) figure 2 shows the RD74VT1G245 used in a bidirectional logic level?shifting application. since the RD74VT1G245 does not have an output enable (oe) pin, the system designer should take pr ecautions to avoid bus contention between system?1 and system?2 when changing directions. 6 1 5 4 2 3 system?1 system?2 pullup/down or bus?hold* dir ctrl i/o?1 i/o?2 v cc1 v cc1 v cc2 pullup/down or bus?hold* v cc2 notes: following is a sequence that illustrates data transmission from system?1 to system?2 and then from system?2 to system?1. 3 4 2 1 l hi?z system?2 is getting ready to send data to system?1. i/o?1 and i/o?2 are disabled. the bus?line state depends on pull?up or down.* dir bit is flipped. i/o?1 and i/o?2 are atill disabled. the bus?line state depends on pull?up or down.* h in h system?1 data to system?2 system?2 data to system?1 hi?z out hi?z out hi?z in l i/o?2 description i/o?1 dir ctrl state *: system?1 and system?2 must use same conditions, i.e., both pull?up or both pull?down. figure 2. bidirectional logic level-shifting application calculate the enable times for the RD74VT1G245 using the following formulas: 1. t zh (dir to a) = t lz (dir to b) + t plh (b to a) 2. t zl (dir to a) = t hz (dir to b) + t phl (b to a) 3. t zh (dir to b) = t lz (dir to a) + t plh (a to b) 4. t zl (dir to b) = t hz (dir to a) + t phl (a to b) in a bidirectional application, these enable times provide the maximum delay from the time the dir bit is switched until an output is expected. for example, if the RD74VT1G245 initially is transmitting from a to b, then the dir bit is switched, the b port of the device must be disabled before presenting it with an input. after the b port has been disabled, an input signal applied to it appears on the corresponding a port after the specified propagation delay.
RD74VT1G245 rev.1.00 jan. 13, 2005 page 13 of 13 package dimensions tbs-6av eiaj package code jedec code mass (g) lead material 0.001 ?? ? symbol dimension in millimeters min nom max a 0.50 0.185 (0.315)* 0.05 0.05 0.20 0.25 0.90 1.40 0.50 0.20 0.20 0.20 0.155 a 1 a 2 b d e e x y 1 y zd ze e e d zd ze e a1 a2 a c b a 12 pin #1 index area c c b seating plane 6 b c x m a b c x m y 1 // c y c *reference value.
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